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Qucs

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  Analyzed 4 days ago

Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations. DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and ... [More] simulations are supported thanks to integration with FreeHDL and Icarus Verilog. Output is may be presented with wide variety of graph and tabular charts. The package consists of two utilities: Qucs, elegant and powerfull GUI for designing and simulating circuits, with point-and-click interface, based on Qt® by Digia®. Qucsator, a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. May also be used by applications other than [Less]

462K lines of code

8 current contributors

almost 3 years since last commit

10 users on Open Hub

Inactive
4.66667
   
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GHDL

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  Analyzed 4 days ago

GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL provides full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 revision. GHDL allows you to analyse and ... [More] elaborate sources for generating machine code from your design. [Less]

878K lines of code

18 current contributors

6 days since last commit

9 users on Open Hub

High Activity
4.66667
   
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VUnit HDL

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  Analyzed 1 day ago

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing ... [More] methodologies by supporting a "test early and often" approach through automation. [Less]

79.3K lines of code

25 current contributors

6 days since last commit

3 users on Open Hub

Moderate Activity
5.0
 
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OSVVM

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  Analyzed 2 days ago

Open Source VHDL Verification Methodology (OSVVM) is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as ... [More] needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models. [Less]

110K lines of code

1 current contributors

5 days since last commit

3 users on Open Hub

Moderate Activity
5.0
 
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HDMI2USB

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Claimed by TimVideos.us - Live Event S... Analyzed 5 months ago

Hardware based on a Xilinx Spartan 6 FPGA for capturing HDMI and DVI data.

121M lines of code

13 current contributors

about 4 years since last commit

2 users on Open Hub

Activity Not Available
0.0
 
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pyVHDLModel

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  Analyzed 6 days ago

An abstract language model of VHDL written in Python.

6.61K lines of code

0 current contributors

5 months since last commit

2 users on Open Hub

Very Low Activity
5.0
 
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Electronic Design Automation Abstraction (EDA²)

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  Analyzed 4 days ago

38.8K lines of code

0 current contributors

about 1 month since last commit

2 users on Open Hub

Moderate Activity
0.0
 
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Licenses: No declared licenses

PicoBlaze-Library

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  Analyzed 4 days ago

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

15.6K lines of code

0 current contributors

over 8 years since last commit

1 users on Open Hub

Inactive
5.0
 
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PoC-Library

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  Analyzed 3 days ago

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

52.9K lines of code

2 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
5.0
 
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schifra

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  Analyzed about 6 hours ago

Schifra is a very robust, highly optimized and extremely configurable Reed-Solomon error correcting code library for both software and IP core based applications with implementations in C++ and VHDL. Schifra supports standard, shortened and punctured Reed-Solomon codes. It also has support for ... [More] stacked product codes and interleaving. General Features * Errors and Erasures * Supported Symbol Sizes - 2 to 32 bits * Variable Code Block Length * User defined primitive polynomial and finite field * Accurate and Validated Reed-Solomon Codecs - Complete combinatorial errors and erasures unit testing [Less]

7.44K lines of code

1 current contributors

over 4 years since last commit

1 users on Open Hub

Inactive
5.0
 
I Use This